1. Field of the Invention
The present invention is directed to integrated circuit design software used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to a method of statistical timing analysis of an integrated circuit design.
2. Description of Related Art
In a previous design flow used in the manufacture of integrated circuits, timing closure is performed for the integrated circuit design using a static timing analysis (STA) tool to find timing critical paths. A path is timing critical, for example, if it has a timing slack that is less than some positive limit, that is, the propagation delay of the path may not meet setup or hold time specifications due to the effect of crosstalk delay.